1. Field
The following description relates to circuit design. Also, the following description relates to circuits that are Complementary Metal-Oxide-Semiconductor (CMOS) switch circuit, and also to a CMOS analog switch circuit configured to suppress substrate effects from generating due to a voltage difference between substrate and source terminals and to maintain substrate (body) voltage to ground voltage (vss) state irrespective of whether supply voltage (vdd) is applied or not. For example, the description includes biasing the substrate voltage of a transistor operating as a switching device.
2. Description of Related Art
Analog switches switch on and off an analog signal in accordance with an external control signal. To ensure normal on/off operation, the control signal avoids inappropriate signal information.
To design an analog switch, a Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET, referred to subsequently as “MOS”) with small drive power and excellent switching speed is used.
A few examples of an analog switch designed using MOS technology will be explained below.
FIG. 1 is a circuit diagram of a CMOS analog switch designed according to related approaches.
The analog switch illustrated in FIG. 1, in particular, has two MOS. That is, NMOS and PMOS, differing from each other, are connected in parallel to each other.
The gates of the NMOS and PMOS are each connected to a control terminal to apply a control signal. The control terminal provides a high control signal or a low control signal to set the switch as being on or off.
The drains and sources of the NMOS and PMOS act as nodes of the switch on both sides of the switch.
In the analog switch 10 with an architecture as explained above and illustrated in FIG. 1, a signal is conducted or isolated in accordance with a control signal applied to the NMOS and the PMOS. Hence, an application of a high control signal to the NMOS and a low control signal to the PMOS causes formation of appropriate channels using the appropriate carriers in the NMOS and the PMOS. Because the channels form, the application of such control signals permits a signal to pass. By contrast, the application of a low control signal to the NMOS and a high control signal to PMOS causes the NMOS and PMOS to turn into cut-off state at which a signal is blocked.
Since supply voltage level is directly applied to the sources of the NMOS and the PMOS of the particular example of an analog switch as illustrated in FIG. 1, such direct application of a supply voltage level creates a voltage difference between the substrate and the sources. This is called a substrate effect, which has an impact on certain characteristics of the analog switch illustrated in FIG. 1. For example, the substrate effect increases a threshold voltage of MOS and also increases conduction resistance of the switch. Increased threshold voltage in the transistor increases power consumption. Furthermore, increased conduction resistance hinders normal on and off switching operation of the transistor. Furthermore, the substrate effect also interferes with the linear characteristic and the harmonic distortion of an analog switch.
Another related approach to designing an analog switch with a different circuit construction to deal with the above-mentioned problems has been suggested. Such an analog switch will be explained below with reference to FIG. 2.
FIG. 2 is a circuit diagram of another related analog switch with a different design than the switch of FIG. 1.
The analog switch 20 of FIG. 2 uses a total of three MOS, where the MOS in FIG. 2 are all of the same type of MOS. That is, the analog switch 20 of FIG. 2 includes a NMOS 1 for providing switching function. FIG. 2 also includes NMOS 2 and NMOS 3 that are provided to bias the substrate voltage of NMOS 1 to help manage the substrate effect discussed previously.
The gate of NMOS 1 is connected to the control terminal 22, while the source and the drain of NMOS 1 are terminals of NMOS 1 on both sides that are involved with the on and off switching operation of NMOS 1. For example, the drain-side terminal switches off NMOS 1, while the source-side terminal switches on NMOS 1. The gate of NMOS 2 is connected to the control terminal 22, while the source and the substrate of NMOS 2 are connected to a substrate node (a) of NMOS 1. The gate of NMOS 3 is connected to the control terminal 22 via an inverter, the drain of NMOS 3 is connected to the substrate node (a) of NMOS 2, and the source of NMOS 3 is grounded.
The analog switch illustrated in FIG. 2 with the above-explained circuit construction may avoid a substrate effect, because there is no voltage difference generated between the source and substrate of NMOS 1 when it operates as a switch, due to the other components of the analog switch.
Thus, when a high control signal is generated from the control terminal 22, both NMOS 1 and NMOS 2 turn on. Accordingly, a channel for signal transmission is formed. However, NMOS 3 remains in an off state, because a low control signal is applied to it by the inverter, which inverts the control signal from the control terminal 22.
Since the source and the substrate of NMOS 3 are connected to the substrate node (a) of NMOS 1, the voltage level of node (b), to which the drain of the first NMOS and the drain of the second NMOS are connected, is directly transmitted to the substrate node (a).
As a result, the source and the substrate of NMOS 1 do not have a voltage difference. Therefore, no substrate effect occurs.
However, the example of FIG. 2 is limited to functioning only in situations when supply voltage (vdd) is successfully fed.
Accordingly, when the supply voltage (vdd) is not successfully applied, other issues with the operation of the switch occur. That is, in situations where the switch operates without the application of the supply voltage, both the control terminal 22 and the drain-side terminal of NMOS 1 assume a ground voltage (vss) level. As a result, since both the control terminal 22 and the drain-side terminal of NMOS 1 assume a ground voltage (vss) level, it leaves the substrate node (a) in floating state. As a result, when the substrate node (a) is not turned to ground voltage (vss) level because it is in a floating state, NMOS 1 enters into unstable state. In such an unstable state, latch-up and leakage current from the switch may occur.